1. Field of the Invention
The invention relates generally to the field of computer networking devices. More particularly, the invention relates to a pipelining mechanism which provides for the early availability of switching information for purposes of increasing switch fabric throughput.
2. Description of the Related Art
With Local Area Network (LAN) switches now operating at data transfer rates of up to 1 Gigabit per second (Gbps), switching capacity in terms of switch fabric throughput is of critical importance.
As used herein, the terms Ethernet, Fast Ethernet, and Gigabit Ethernet shall apply to Local Area Networks (LANs) employing Carrier Sense, Multiple Access with Collision Detection (CSMA/CD) as the medium access method, generally operating at a signaling rate of 10 Megabits per second (Mbps), 100 Mbps, and 1,000 Mbps, respectively over various media types and transmitting Ethernet formatted or Institute of Electrical and Electronic Engineers (IEEE) standard 802.3 formatted data packets.
With reference to the simplified block diagram of FIG. 1, an approach for managing access to a switch memory will now briefly be described. Switch 100 includes a switch memory 110 coupled to a plurality of port interfaces 105-108 and a memory manager 115. The switch memory 110 may temporarily buffer packets received from the port interfaces 105-108 until the one or more ports to which the packets are destined are prepared to transmit the data. In this example, the memory manager 115 may coordinate the allocation of portions (buffers) of the switch memory 110 for packet storage and maintain a mapping of some sort to associate the buffers with a port (e.g., the source or destination port). That is, the buffers of the switch memory 110 may be physically or logically organized to facilitate data storage and retrieval. In any event, the memory manager 115 may additionally arbitrate the interface between the port interfaces 105-108 and the switch memory 110. For instance, the memory manager 115 may employ various mechanisms to determine which of the port interfaces 105-108 have data to transfer into the switch memory, which of the port interfaces 105-108 are prepared to receive data from the switch memory, and which port interface 105-108 may access the switch memory 110 during a particular clock cycle.
In order to maintain the integrity of the physical or logical organization of the switch memory 110, it is typically necessary for the memory manager 115 to examine a portion of the packet (e.g., the source or destination port, and/or other packet forwarding control information) prior to storing the packet data in the switch memory 110. For example, the memory manager may need to determine where to store the packet data based upon the packet's contents and if space is available in the particular physical or logical bin to which the packet data maps. Therefore, the memory manager 115 is provided with access to a subset, M, of the N data lines comprising data bus 120. In this manner, the memory manager 115 may determine the appropriate processing required for storing the packet data on data bus 120.
Several difficulties arise using the above switch memory access approach. For instance, the processing required to be performed by the memory manager 115 on the portion of the packet may require more than one memory clock cycle to complete. If this is the case, two options would appear to be available in this switch architecture. The first option is to slow down the memory clock relative to the clock domain of the memory manager 115 such that the memory manager 115 is able to complete its worst case processing within a memory clock cycle. The second option is to simply read the packet data twice, once to provide the packet data to the memory manager 115 and a second time, after the memory manager 115 has completed its processing, to transfer the packet data from the port interface 105-108 to the switch memory 110. However, both of these options result in the inefficient utilization of the data bus 120. Consequently, the packet forwarding rate through the switch memory 110 is negatively impacted.